The present invention relates to an integrated circuit, and in particular to an integrated circuit which contains a coaxial signal line formed at least partially within a silicon-containing substrate. Specifically, the inner conductor of the coaxial signal line of the present invention is formed within the silicon-containing substrate and it is completely surrounded by an insulator. The design of the coaxial signal line of the present invention provides a device with increased speed, impedance matching and a high signal quality. The present invention also provides a method of forming an integrated circuit which contains the coaxial signal line of the present invention therein as well as interconnect structures wherein the integrated circuit is connected through the coaxial wiring to an external substrate such as a printed circuit board (PCB).
As semiconductor devices become faster and faster, silicon-on-insulator (SOI) devices are becoming more common. In such SOI devices, the signal wiring needs to increase its speed and signal quality. Printed circuit boards typically employ a strip line structure to improve the signal quality.
Typical prior art strip line structures are shown in FIGS. 1(a)-(b). Specifically, the strip line structure comprises a substrate 2, a signal wiring pattern 4, a dielectric 6 and a conductor 8 or 10. In FIG. 1(a), the signal wiring pattern 4 is formed on substrate 2, dielectric 6 is formed on substrate 2 covering the wiring pattern and an upper conductor 8, which functions as a power supply wiring layer or grounded layer, is formed above wiring pattern 4. In FIG. 1(b), signal wiring pattern 4 is formed on dielectric 6 and above substrate 2, a lower conductor 10 having the above mentioned function is formed below wiring pattern 4 and on substrate 2.
Other strip line structures besides those mentioned above are also known. Common to all prior art strip line structures is that one or more layers of conductors are located between the wiring pattern and the dielectric.
One problem with prior art strip line structures is that the signal wiring pattern is not completely surrounded by an insulator. That is, prior art strip line structures are not completely insulated from external conductors. This results in electrical signal leaks from the signal wiring pattern and crosstalk noise is generated due to the influence between adjacent wiring patterns. Also, mismatch of the characteristic impedance occurs.
One solution to this problem is mentioned in U.S. Pat. No. 5,357,138 to Kobayashi. In the Kobayashi disclosure, the coaxial wiring structure comprises a substrate; a grounded lower conductive layer formed on said substrate; a lower dielectric layer selectively formed on said lower conductive layer; a signal wiring pattern selectively formed on the lower dielectric layer; an upper dielectric layer formed of a photosensitive dielectric material on said signal wiring pattern and the lower dielectric layer so as to cover the signal wiring pattern provided on the lower dielectric layer; a grounded upper conductive layer formed on the upper dielectric layer; and grounded conductive layers extending between the upper and lower conductive layers which are disposed in spaces formed in the lower dielectric layer.
Despite the structure provided in the Kobayashi disclosure, there is a need to provide new and improved coaxial wiring structures which can be employed in high speed operations, yet exhibit a high signal quality.
An object of the present invention is to provide coaxial wiring which can be employed in high speed operations without loss of any signal quality.
Another object of the present invention is to provide coaxial wiring in which matching of the characteristic impedance is improved and crosstalk is reduced.
A further object of the present invention is to provide coaxial wiring which can be employed within a silicon-containing substrate such as a silicon layer formed as part of a silicon-on-insulator (SOI) device or bulk silicon.
A still further object of the present invention is to provide a semiconductor structure having a fully shielded conductor wherein the shield may be at any potential.
These and other objects and advantages are obtained by using the integrated circuit described hereinbelow. Specifically, the integrated circuit of the present invention comprises a silicon-containing substrate; and a coaxial signal line formed at least partially within said silicon-containing substrate, said coaxial signal line comprising an inner conductor having a length, said length axially surrounded by, and insulated from, an outer conductor along said length.
Another aspect of the present invention relates to interconnect structures which comprise at least the integrated circuit of the present invention connected to an external system such as a printed circuit board, flexible card or a second integrated circuit or chip. The interconnection may be made through a C4 solder, an insulating socket or a C4 coaxial socket. The interconnection may or may not be self-aligned.
A further aspect of the present invention relates to a method of fabricating the above described integrated circuit. Specifically, the method of the present invention comprises the steps of:
(a) forming a trench partially within a silicon-containing substrate of a preformed semiconductor structure;
(b) forming sidewall spacers in said trench;
(c) forming a first metal layer over said structure provided in (b);
(d) forming a first insulating layer over said first metal layer;
(e) forming a second metal layer over said first insulating layer;
(f) planarizing the structure formed in (e) down to said trench;
(g) forming a second insulating layer over said planarized structure;
(h) patterning said second insulating layer so as to expose a region of said second metal layer and at least one active device region of said preformed semiconductor structure;
(i) forming a third metal layer over the structure provided in (h); and
(j) patterning the same so as to form a means of contacting the active device region within said preformed semiconductor structure with the second metal layer.
In an alternative embodiment of the present invention, steps (h), (i) and (j) above are replaced with: (hxe2x80x2) patterning said second insulating layer so as to expose said first metal layer; (ixe2x80x2) forming a third metal layer over said second insulating layer and exposed areas of said first metal layer; and (jxe2x80x2) patterning the third metal layer and said second insulating layer so that said third metal layer is in contact with the first metal layer but is insulated from the second metal layer by said second insulating layer.
The above processing steps may be repeated any number of times to provide two or more chips interconnected to each other. In an optional embodiment of the present invention, an oxide is deposited on the bottom of the trench prior to depositing the first metal layer.
In another aspect of the present invention, a second level electrical circuit assembly is provided. In accordance with this aspect of the present invention, the second level electrical circuit assembly comprises:
a substrate selected from the group consisting of a circuit card, a circuit board, ceramic and glass; and
a coaxial signal line formed at least partially within the substrate, said coaxial signal line comprising an inner conductor having a length, said length axially surrounded by, and insulated from, an outer conductor along said length.
The above assembly can be used with the integrated circuit described above or it can be connected to an external coaxial circuitry or to a coaxial cable by a C4 coaxial socket, an insulated coaxial socket or a xcexcBNC coaxial socket.
A method of forming such a second level electrical circuit assembly is also disclosed herein. Specifically, the method of forming the assembly comprises:
(a) forming a first metal layer on one of the above substrates;
(b) forming a first insulating layer on said first metal layer;
(c) forming a second metal layer on the first insulating layer;
(d) forming a second insulating layer along a center line of said second metal layer so that it covers the second metal layer entirely and adheres to the first metal layer; and
(e) forming a third metal layer along center line and over the second insulating layer.